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 NTD80N02 Power MOSFET
24 V, 80 A, N-Channel DPAK
Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.
Features
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V(BR)DSS 24 V RDS(on) TYP 5.0 mW ID MAX 80 A
* Pb-Free Packages are Available
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Typical Applications
* * * *
Power Supplies Converters Power Motor Controls Bridge Circuits
G Unit Vdc Vdc Adc 4 Watts C mJ 12 3
N-Channel D
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TC = 25C Drain Current - Single Pulse (tp = 10 ms) Total Power Dissipation @ TC = 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 24 Vdc, VGS = 10 Vdc, IL = 17 Apk, L = 5.0 mH, RG = 25 ) Thermal Resistance - Junction-to-Case - Junction-to-Ambient (Note 1) - Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS ID IDM PD TJ, Tstg EAS Value 24 20 80* 200 75 -55 to 150 733
S
4 4 12 3 12 3
C/W RJC RJA RJA TL 1.65 67 120 260 C
CASE 369C CASE 369D CASE 369AA DPAK DPAK DPAK (Surface Mount) (Surface Mount) (Straight Lead) STYLE 2 STYLE 2 STYLE 2
MARKING DIAGRAMS & PIN ASSIGNMENTS
4 Drain YWW 80 N02 3 Source 1 Gate 2 Drain 3 Source = Year = Work Week = Device Code Publication Order Number: NTD80N02/D 4 Drain
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). *Chip current capability limited by package.
1 Gate
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
December, 2004 - Rev. 4
YWW 80 N02 2 Drain Y WW 80N02
ORDERING INFORMATION
NTD80N02
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Positive Temperature Coefficient Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 24 Vdc) (VGS = 0 Vdc, VDS = 24 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Negative Threshold Temperature Coefficient www..com Drain-to-Source On-Resistance (Note 3) Static (VGS = 10 Vdc, ID = 80 Adc) (VGS = 4.5 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 4.5 Vdc, ID = 20 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 3) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge Ga e C a ge (VGS = 4.5 Vdc, 4 5 Vdc VDD = 20 Vdc, ID = 20 Adc, 2.5 RG = 2 5 ) (VGS = 4.5 Vdc, ID = 20 Adc, VDS = 20 Vdc) (Note 3) td(on) tr td(off) tf QT Q1 Q2 - - - - - - - 17 67 28 40 30 7.0 18 30 125 45 75 42 12 28 nC ns (VDS = 20 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss Coss Crss - - - 2250 900 400 2600 1100 525 pF gFS VGS(th) 1.0 - RDS(on) - - - - 5.0 7.5 5.0 7.5 20 5.8 9.0 5.8 9.0 - Mhos 1.9 -3.8 3.0 - Vdc mV/C m V(BR)DSS 24 - IDSS - - IGSS - - - - 1.0 10 100 nAdc 27 25 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 40 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time e e se eco e y e (IS = 20 Adc, VGS = 0 Vdc, Ad Vd dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. VSD - - - trr ta tb Qrr - - - - 0.92 1.05 0.70 38 20 18 0.038 1.2 - - 52 - - - mC ns s Vdc
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2
NTD80N02
100 90 ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 0 www..com 0.5 1 1.5 2 2.5 3 3.5 4 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 3.4 V 3.2 V VGS = 3.0 V 6.5 V 9V 8V 4.4 V 4.6 V 4.8 V 5V 5.2 V 6V TJ = 25C 4.2 V 4V 3.8 V 3.6 V 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 VDS 24 V
ID, DRAIN CURRENT (AMPS)
TJ = 25C
TJ = 125C TJ = -55C 2 3 4 5 6
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 10 VGS, GATE-TO-SOURCE VOLTAGE (V) ID = 10 A TJ = 25C
RDS(on), DRAIN-TO-SOURCE RESISTANCE ()
0.015 TJ = 25C
0.01
VGS = 4.5 V
VGS = 10 V 0.005
0 55
60
65
70
75
80
ID, DRAIN CURRENT (A)
Figure 3. On-Resistance versus Gate-To-Source Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE 0.015 0.0125 IDSS, LEAKAGE (nA) 0.01 0.0075 0.005 0.0025 0 -50 ID = 80 A VDS = 10 V ID = 80 A VDS = 4.5 V
Figure 4. On-Resistance versus Drain Current and Gate Voltage
1000 VGS = 0 V 100 TJ = 125C TJ = 100C 10
1 TJ = 25C 0.1
-25
0
25
50
75
100
125
150
0.01
4
8
12
16
20
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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3
NTD80N02
-VDS, DRAIN-TO-SOURCE VOLTAGE (V)
5000
VGS, GATE-TO-SOURCE VOLTAGE (V)
VGS = 0 V TJ = 25C
10 28 8 VD Q1 Q2 QT VGS 24 20 16 4 12 8 2 ID = 1.0 A TJ = 25C 0 0 10 20 30 40 50 4 0
C, CAPACITANCE (pF)
4000
3000 Ciss 2000 Coss 1000 Crss
6
0 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 VGS VDS www..com GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
1000 IS, SOURCE CURRENT (AMPS) VDD = 20 V ID = 20 A VGS = 10 V t, TIME (ns) 100 tr tf td(off) td(on)
80 70 60 50 40 30 20 10 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 VSD, SOURCE-TO-DRAIN VOLTAGE (V) VGS = 0 V TJ = 25C
10
1 1 10 RG, GATE RESISTANCE () 100
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
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4
NTD80N02
100 ID , DRAIN CURRENT (AMPS) 100 ms di/dt VGS = 10 V SINGLE PULSE TC = 25C 1 ms IS trr ta 10 ms dc tp IS 10 100 0.25 IS tb TIME
10
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) www..com
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Diode Reverse Recovery Waveform
1000 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE DUTY CYCLE 100 D = 0.5 0.2 0.1 0.05 0.02 0.01
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
10
1
P(pk) t2 DUTY CYCLE, D = t1/t2 1E-03 1E-02 1E-01 t, TIME (seconds) 1E+00 t1
0.1 SINGLE PULSE 0.01 1E-05 1E-04
RJA(t) = r(t) RJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TA = P(pk) RJA(t) 1E+02 1E+03
1E+01
Figure 13. Thermal Response - Various Duty Cycles ORDERING INFORMATION
Order Number NTD80N02 NTD80N02G NTD80N02T4 NTD80N02T4G NTD80N02-001 NTD80N02-1G NTD80N02-032 NTD80N02-032G Package DPAK-3 DPAK-3 (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) DPAK-3 Straight Lead DPAK-3 Straight Lead (Pb-Free) DPAK-3 Straight Lead (3.2 0.5 mm) DPAK-3 Straight Lead (3.2 0.5 mm) (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail 75 Units / Rail 75 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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5
NTD80N02
PACKAGE DIMENSIONS
DPAK CASE 369AA-01 ISSUE O
-T- B V R
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
C E
A S www..com
1 2 3
Z U
F L D
2 PL
J
DIM A B C D E F J L R S U V Z
0.13 (0.005)
M
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228
3.0 0.118
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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6
NTD80N02
PACKAGE DIMENSIONS
DPAK CASE 369C-01 ISSUE O
-T- B V R
4
SEATING PLANE
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 ---
www..com S
A
1 2 3
Z U
K F L D G
2 PL
J H 0.13 (0.005) T
DIM A B C D E F G H J K L R S U V Z
M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
SOLDERING FOOTPRINT*
6.20 0.244 2.58 0.101 5.80 0.228
3.0 0.118
1.6 0.063
6.172 0.243
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
NTD80N02
PACKAGE DIMENSIONS
DPAK CASE 369D-01 ISSUE B
B V R
4
C E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ---
Z A
3
S -T-
SEATING www..com PLANE
1
2
K
F D G
3 PL
J H 0.13 (0.005)
M
DIM A B C D E F G H J K R S V Z
T
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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8
NTD80N02/D


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